It was originally a language proprietary to Cadence Design Systems (http://www.cadence.com/) for use with their logic simulators[?], but the increasing success of VHDL prompted Cadence to move down the Open Standards[?] route, and Verilog is now IEEE Standard 1364.
Verilog has a syntax reminiscent of C, which helps explain its rapid take up among engineers who had already learnt to use that language. It is case-sensitive.
An example counter circuit follows:
module Div20x (rst, clk, cet, cep, count,tc); //TITLE 'Divide-by-20 Counter with enables' //enable CEP is a clock enable only //enable CET is a clock enable and enables the TC output //a counter using the Verilog language parameter size = 5; parameter length = 20; input rst; input clk; input cet; input cep; output [size-1:0] count; output tc; reg [size-1:0] count; wire tc; always @ (posedge rst or posedge clk) begin if (rst) count = 5'b0; else if (cet && cep) begin if (count == length-1) begin count = 5'b0; end else count = count + 1; end end assign tc = (cet && (count == length-1)); endmodule
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