VHSIC Hardware Description Language

VHDL or VHSIC Hardware description language is commonly used as a design-entry language for FPGAs and ASICs.

Brief History

VHDL was originally developed at the behest of the US Department of Defense in order to document the behaviour of the ASICs that supplier companies were including in equipment. As should be obvious from the example code below, VHDL has a syntax similar to Pascal and Ada, thus being a descendant of Algol. VHDL is case-insensitive[?].

The idea of being able to simulate this behaviour was so obviously attractive that logic simulators[?] were developed that could read the VHDL files. The next step was the development of logic synthesis[?] tools that read the VHDL, and output a definition of the physical implementation of the circuit. Modern synthesis tools can extract RAM, counter, and arithmetic blocks out of the code, and implement them in the way most efficient in the intended technology.

The initial version of VHDL, to standard IEEE 1076-1987, included a wide range of data types, including numerical (integer and real), logical (bit and boolean), character and time, plus arrays of bit called bit_vector and of character called string.

A problem not solved by this edition, however, was "multi-valued logic", where a signal's drive strength (none, weak or strong) and unknown values are also considered. This required IEEE standard 1164[?], which defined the 9-value std_logic.

The second issue of IEEE 1076[?], in 1993, made the syntax more consistent, allowed more flexibility in naming, extended the character type match the full 8-bit ASCII definition, added the xnor operator, etc.

More recently, the language has been extended by introducing

• signed and unsigned types to facilitate arithmetical operations;
• analog(ue) and mixed-signal circuit design extensions;
• VITAL (VHDL Initiative Towards ASIC Libraries);
• microwave circuit design extensions.

Discussion

VHDL is in fact a fairly general-purpose programming language, provided that you have a simulator on which to run the code. It can read and write files on the host computer - this author has written a VHDL program(me) that generated another VHDL program(me) to be incorporated in the design being developed. Because of this general-purpose nature, it is possible use VHDL to write a testbench that verifies the functionality of the design, using files on the host computer to define stimulus, interacts with the user, and compares results with those expected. In this regard, it is considered by some to be superior to Verilog. However, it is easy for the unwary and inexperienced to produce code that simulates successfully, but that cannot be synthesized into a real device, or else is too large to be practicable. A particular pitfall is producing transparent latches rather than D-type flip-flops as storage elements.

Code Examples

These are written in VHDL-93 with its more consistent syntax.

Hello World

The canonical first program(me) example:

  --  VHDL example programme: hello.vhd

  use std.textio.all;

  entity hello is
  end entity hello;

  architecture Wiki of hello is

      constant message : string := "hello world";

  begin

      process is
          variable L: line;
      begin
          write(L, message);
          writeline(output, L);
          wait;
      end process;

  end architecture Wiki;

The intended message is output to the simulator's default output window.

Fibonacci Series

The following example is a little more real-world:

  --  Fib.vhd
  --
  --  Fibonacci number sequence generator

  library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.numeric_std.all;

  entity Fibonacci is
  port
  (
      Reset       : in    std_logic;
      Clock       : in    std_logic;
      Number      : out   unsigned(31 downto 0)
  );
  end entity Fibonacci;

  architecture Rcingham of Fibonacci is

      signal  Previous    : natural;
      signal  Current     : natural;
      signal  Next_Fib    : natural;

  begin

      Adder:

      Next_Fib <= Current + Previous;

      Registers:
      process (Clock, Reset) is
      begin
          if Reset = '1' then
              Previous <= 1;
              Current  <= 1;
          elsif Clock'event and Clock = '1' then
              Previous <= Current;
              Current  <= Next_Fib;
          end if;
      end process Registers;

      Number <= to_unsigned(Previous, 32);

  end architecture Rcingham;

When simulated, it generates the Fibonacci sequence successfully, until Next_Fib overflows the range of the natural type.

When synthesized with an FPGA vendor's tools, an "Adder" module was implemented, as hoped for. Otherwise, the assignment statement would have to be replaced by a component instantiation to logic that implements that function.

External Links

• contains lots of useful information including a FAQ (http://www.eda.org/)
• The FAQ of news://comp.lang.vhdl (http://www.vhdl.org/comp.lang.vhdl/)
• VHDL International (http://www.accellera.org/)
• VHDL'87 syntax as Hypertext (http://opensource.ethz.ch/emacs/vhdl87_syntax)
• VHDL'93 syntax as Hypertext (http://opensource.ethz.ch/emacs/vhdl93_syntax)
• VHDL-AMS syntax as Hypertext (http://opensource.ethz.ch/emacs/vhdlams_syntax)
• IEEE standard 1164 (http://www.acc-eda.com/vhdlref/refguide/language_overview/using_standard_logic/ieee_standard_1164.htm)
• Peter Ashenden's "VHDL Cookbook" (in VHDL-87) (http://www.ecsi.org/EARNEST/digests/VHDL_cookbook/default.htm)