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MIPS architecture

MIPS, an acronym for Microprocessor without Interlocked Pipeline Stages, is a microprocessor architecture developed by MIPS Computer Systems Inc.

The MIPS CPU family was one of the most successful and flexible CPU designs throughout the 1990s, and has found broad application in embedded systems, Windows CE devices, SGI workstations, and Cisco Internet routers. The Nintendo 64 video game console uses a 64-bit MIPS processor.

The MIPS CPU features a five-stage CPU pipeline to execute multiple instructions at the same time. The CPU has 32 registers, from which two serve special purposes, the rest being available to generic use, regulated through ABI conventions. Popular compilers that target the MIPS architecture include the MIPSPro Compiler and GCC.

Four backward-compatible revisions of the MIPS instruction set exist, named MIPS I to MIPS IV. Because the designers created such a clean instruction set (see Instructions[?]), computer architecture courses in universities and technical schools often study the MIPS architecture. The design of the MIPS CPU family, together with SPARC, another early RISC architecture, greatly influenced later RISC designs like HP Precision Architecture[?] and Alpha.

The early MIPS architectures were 32-bit implementations (generally 32 bit wide registers and data paths), later versions were 64-bit implementations.

Table of contents

History of the MIPS CPU family

In 1984, researchers at Stanford University created the first MIPS processor. The basic concept was to dramatically increase possible clock speeds by dramatically reducing the number of potential delays in the instruction paths. Each instruction could take only one cycle to complete, and by imposing this limitation, the system could be run much faster due to the absence of locks between parts of the chip, which take time to set up. Of course this eliminated complex instructions like multiply, and the MIPS is one of the first RISC designs.

The first commercial MIPS CPU, model, the R2000, was announced in 1985. It added multiply and divide by including a separate unit for these tasks. In order to do this, the system inserted special "delay slots" into the instruction stream, filling them with other instructions that would complete in one cycle. The instructions were then re-ordered on the way out. The R2000 also had support for up to 4 co-processors, one of which was built into the main CPU and handled exceptions and traps, while the other three were left for other uses. One of these could be filled by the optional R2010 FPU, which had thirty-two 32-bit registers that could be used as sixteen 64-bit registers for double-precision.

The R3000 succeeded the R2000 in 1988, adding 32kB caches for instructions and data, 64kB total, along with cache coherency support for multi-processor use. However, it turned out that the multiprocessor support was flawed, and the R3000 was not widely used in this way. The R3000 also included a built-in MMU, a common feature on CPUs of the era.

The R4000 series, released in 1991, changed the MIPS line to a full 64-bit implementation, and moved the FPU onto the main die to create a single-chip system. However, this left little room, so the caches were reduced to 8kB each. With the introduction of the R4000 a number of improved versions soon followed, including the R4400 of 1993 which included 16kB caches and a controller for another 1MB external (level 2) cache, and the R4600, a speed-bumped R4400, later that same year. A modified version of the R4000 core was used in the Nintendo 64.

The R5000 increased caches to 32kB each, and had certain optimizations over the earlier R4000s that allowed faster graphics processing; mostly, this amounted to the FPU being optimized for single precision. R5000-based SGI Indys had much better graphics performance than similarly clocked R4400 Indys with the same graphics hardware. SGI gave the old graphics board a new name when it was combined with R5000 in order to emphasize the improvement.

The R8000 (1994) was the first superscalar MIPS design, including two R4000-like ALU cores on a single die. This left no room for the FPU, which had to be moved back out to an external chip, and in this now-larger space they included considerably improved performance. The R8000 powered SGI's Power Challenge computer servers in the mid 1990s and later became available in the Indigo2 Impact workstation. Its limited integer performance and high cost dampened appeal for most users, although its FPU performance fit scientific users quite well, and the R8000 was in the marketplace for only a year and remains fairly rare.

The R10000 was the next, and likely last, major step in the MIPS design. Released in 1995 it essentially combined the R8000's two-ALU integer unit with two simplified FPUs on a single die, adding a new out-of-order execution scheduler. Even with the simpler FPU the real performance was better due to faster clock speeds and more cores, and the R10000 quickly replaced all of their earlier designs in SGI hardware.

More recent designs have all been built on the R10000 core. The R12000 used an improved process to shrink the chip and run it at higher clock rates. The R14000 bumped the speed again to up to 600MHz, added support for DDR SRAM in the cache, and increased the computer bus speed to 200MHz for better throughput. The most recent version, the R16000, doubles the size of the caches to 64kB for both the address and data cache, adds support for up to 8MB of level 2 cache, and bumps the clock rates once again, to 700MHz.

Other models and future plans

Other members of the MIPS family include the R6000, a bipolar implementation of the R3000 built by a third party. The R6000 did not deliver the promised performance benefits, and quickly disappeared. The R7000 was a version of the R5000 with a built-in 256kB level 2 cache and a controller for optional level three cache. It was primarily targeted at embedded designs, including SGI's graphics processors and various networking solutions. The R9000 name was never used.

At one time SGI had intended to move off the MIPS platform to the Intel Itanium, and development was to have ended with the R10000. The ever-longer delays in introducing the Itanium meant that the installed base of MIPS-based machines continued to increase. By 1999 it was clear that development had ended too soon, and the R14000 and R16000 were created as a result. SGI has hinted at a more complex R8000 style FPU for later R-series, and a dual core processor is probable. Low power consumption / heat dissipation will continue be a focus.

Further reading

  • Patterson and Hennessy: Computer Organization and Design. The Hardware/Software Interface. Morgan Kaufmann Publishers. ISBN 1-55860-281-X

This book about computer design in general, and RISC in particular, takes its examples directly from the MIPS architecture. No wonder, since Hennessy was an early collaborator in the Stanford project which became MIPS.

MIPS Programing

There is a freely available "MIPS R2000/R3000 Simulator" called SPIM for several operating systems (i.e., UNIX or GNU/Linux; MS Windows 95, 98, NT, 2000, XP; and DOS) which is good for learning MIPS assembler programing and the general concepts of RISC-assembler programing: http://www.cs.wisc.edu/~larus/spim



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