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SPARC (Scalable Processor ARChitecture) is a RISC microprocessor architecture originally designed in 1985 by Sun Microsystems. SPARC CPUs are primarily used in Sun's own product line of workstations and servers and also, to a much lesser extent, in designs from other manufacturers.

The CPUs themselves have been licensed to several manufacturers, including Texas Instruments, Cypress Semiconductor[?], and Fujitsu. Although the SPARC system has ostensibly been an open standard since 1986, in fact the documentation for the system is available only after signing a license and a nondisclosure agreement. Attempts by the OpenBSD group to buy the documentation without such an agreement have been stonewalled.


The SPARC architecture was heavily influenced by the earlier designs of the RISC I & II from the University of California at Berkeley. These original RISC designs were minimalist, including as few features or op-codes as possible and demanding that all operations complete in one cycle. This made them similar to the MIPS architecture in many ways, including the lack of instructions such as multiply or divide.

Unlike the MIPS developers, the SPARC designers decided in favor of aggressive use of "windowed registers" for performance. The basic design included 128 32-bit registers, which can be accessed in "windows" of 8. This made subroutine calls inexpensive: instead of having to save the data from these registers when calling, it simply "moved the window" down and left the original data intact. The architecture has gone through several revisions and has gained multiply and divide functionality along the way.

A more radical upgrade resulted in the 64-bit UltraSPARC. It includes a number of additional units, deeper pipelines, and a series of simple SIMD instructions called VIS. The UltraSPARC standard has gone through three major revisions, the latest being UltraSPARC III.

As of 2002, the current versions are the 32-bit V8 and the 64-bit V9.


Some unusual features of the architecture are:

Windowed register file. A defined number of registers (expected to be much larger than 32) is implemented; at any time 24 of them (the register window) are visible as ordinary instruction-accessible registers. The window can moved up or down the register file under software control.

The floating-point register file can be configured as 32 32-bit registers (single precision) or 16 64-bit registers (double precision) or 8 128-bit registers ("quad precision").

Tagged add and subtract instructions perform adds and subtracts on values assuming that the bottom two bits do not participate in the computation. This can be useful in the implementation of the run time for ML, Lisp, and similar languages that might use a tagged integer format.


Like many RISC architectures, early versions of the architecture had a branch delay slot[?] which sometimes made coding by hand a little bit awkward.

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