SBus is in many ways a "clean" design. It was targetted only to the SPARC so many cross-platform issues were simply not a consideration. SBus was based on a big-endian 32-bit address and data bus, run at 25MHz and thus transfers up to 100Mbyte/second. Devices are each mapped onto a 28-bit address space (16 megabytes), and only eight masters are supported although there are an unlimited number of slaves.
When the 64-bit UltraSPARC was introduced SBus was modified to use clock-doubling and transfer two 32-bit data words per cycle to produce a 200MByte/s 64-bit bus. For contrast, modern 66MHz/64-bit PCI is 528MByte/s.
SBus was a peripheral interconnect only (like PCI). Sun systems used another standardized system as a CPU-memory bus, MBus[?].
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