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Phase-locked loop

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In electronics, a phase-locked loop (PLL) is an electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal.

Phase-locked loops are widely used for synchronization purposes; in space communications for coherent carrier tracking and threshold extension, bit synchronization[?], and symbol synchronization.

Phase-locked loops can also be used to demodulate[?] frequency modulated signals, and to synthesize new frequencies which are a multiple of a reference frequency.

An important part of a phase-locked loop is the phase detector[?]. This compares the phase of the local oscillator to that of the reference signal. In an analogue PLL the phase detector is a linear multiplier. This generates a low-frequency signal whose amplitude is related to the phase difference, or phase error, between the oscillator and the reference, and an unwanted high-frequency signal that is filtered out.

There are several types of phase detectors used in digital phase-locked loops. The simplest is an exclusive OR gate, which maintains a 90° phase difference, but cannot lock the signal unless it is already on frequency. A more complicated one uses flip-flops to determine which of the two signals has a zero-crossing earlier or more often. This brings the signal in even when it is off frequency.

Analog Phase-locked Loop

The equations governing a phase-locked loop are the following:

<math>x_m(t) = x_c(t) \cdot x_r(t)</math>
<math>\omega_r(t) = \omega_f + g_v y(t)</math>
<math>x_r(t) = A_r \cos\left( \int \omega_r(\tau) d\tau \right)
              = A_r \cos(\omega_f t + \phi)</math>
where
<math>\phi = \int g_v y(\tau) d\tau</math>
the input to the the PLL is <math>x_c(t)</math>, the output of the voltage controlled oscillator[?] (VCO) is <math>x_r(t)</math>, the output of the phase detector is <math>x_m(t)</math>. The input to the loop filter is <math>x_m(t)</math>, the output is <math>y(t)</math>. Note that <math>g_v</math> is the sensitivity of the VCO and is expressed in Hz/V.

We can deduce how the PLL reacts to a sinusoidal input signal:

<math>x_c(t) = A_c \sin(\omega_c t).</math>
The output of the phase detector then is:
<math>x_m(t) = A_c \sin( \omega_c t ) A_r \cos(\omega_f t + \phi).</math>
This can be rewritten into sum and difference components using trigonometric identities:
<math>x_m(t) = {A_c A_f \over 2} \sin( \omega_c t - \omega_f t - \phi )
                + {A_c A_f \over 2} \sin( \omega_c t + \omega_f t + \phi )
</math> Filtering out the sum frequency and leaving the difference frequency, enables us to derive a small-signal model of the phase-locked loop. If we can make <math>\omega_f \approx \omega_c</math>, then the <math>\sin(\cdot)</math> can be approximated by its argument: <math>- A_c A_f \phi / 2</math>. The phase-locked loop is said to be locked if this is the case.

Some parts of this article are derived from public domain parts of Federal Standard 1037C in support of MIL-STD-188.



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