Redirected from PLL
Phaselocked loops are widely used for synchronization purposes; in space communications for coherent carrier tracking and threshold extension, bit synchronization[?], and symbol synchronization.
Phaselocked loops can also be used to demodulate[?] frequency modulated signals, and to synthesize new frequencies which are a multiple of a reference frequency.
An important part of a phaselocked loop is the phase detector[?]. This compares the phase of the local oscillator to that of the reference signal. In an analogue PLL the phase detector is a linear multiplier. This generates a lowfrequency signal whose amplitude is related to the phase difference, or phase error, between the oscillator and the reference, and an unwanted highfrequency signal that is filtered out.
There are several types of phase detectors used in digital phaselocked loops. The simplest is an exclusive OR gate, which maintains a 90° phase difference, but cannot lock the signal unless it is already on frequency. A more complicated one uses flipflops to determine which of the two signals has a zerocrossing earlier or more often. This brings the signal in even when it is off frequency.
The equations governing a phaselocked loop are the following:
= A_r \cos(\omega_f t + \phi)</math>where
We can deduce how the PLL reacts to a sinusoidal input signal:
+ {A_c A_f \over 2} \sin( \omega_c t + \omega_f t + \phi )</math> Filtering out the sum frequency and leaving the difference frequency, enables us to derive a smallsignal model of the phaselocked loop. If we can make <math>\omega_f \approx \omega_c</math>, then the <math>\sin(\cdot)</math> can be approximated by its argument: <math> A_c A_f \phi / 2</math>. The phaselocked loop is said to be locked if this is the case.
Some parts of this article are derived from public domain parts of Federal Standard 1037C in support of MILSTD188.
Search Encyclopedia

Featured Article
