Encyclopedia > Pipeline stall

  Article Content

Pipeline break

Redirected from Pipeline stall

A pipeline break (or "pipeline stall") is the delay caused on a processor using pipelines when a transfer of control[?] is taken. Normally when a control-transfer instruction (a branch, conditional branch, call or trap) is taken, any following instructions which have been loaded into the processor's pipeline must be discarded or "flushed" and new instructions loaded from the branch destination. This introduces a delay before the processor can resume execution.

"Delayed control-transfer[?]" is a technique used to reduce this effect.


This article (or an earlier version of it) contains material from FOLDOC, used with permission.



All Wikipedia text is available under the terms of the GNU Free Documentation License

 
  Search Encyclopedia

Search over one million articles, find something about almost anything!
 
 
  
  Featured Article
Photosynthesis

... is used to drive a transfer of electrons and hydrogen from water (or some other donor molecule) to an acceptor called NADP[?]+, reducing it to the form of NADPH by adding a ...

 
 
 
This page was created in 22.9 ms