Encyclopedia > Pipeline break

  Article Content

Pipeline break

A pipeline break (or "pipeline stall") is the delay caused on a processor using pipelines when a transfer of control[?] is taken. Normally when a control-transfer instruction (a branch, conditional branch, call or trap) is taken, any following instructions which have been loaded into the processor's pipeline must be discarded or "flushed" and new instructions loaded from the branch destination. This introduces a delay before the processor can resume execution.

"Delayed control-transfer[?]" is a technique used to reduce this effect.


This article (or an earlier version of it) contains material from FOLDOC, used with permission.



All Wikipedia text is available under the terms of the GNU Free Documentation License

 
  Search Encyclopedia

Search over one million articles, find something about almost anything!
 
 
  
  Featured Article
242

... - 4th century Decades: 190s 200s 210s 220s 230s - 240s - 250s 260s 270s 280s 290s Years: 237 238 239 240 241 - 242 - 243 244 245 246 247 Events Patriarch ...

 
 
 
This page was created in 39 ms