IBM 1620 Model II

It had basic ALU hardware for Addition and Subtraction, but Multiplication was still done by table lookup in Core memory. Multiplication used a 200 digit table (@ address 00100..00299). The Divide hardware using a repeated Subtraction algorithm, was built in. Floating Point arithmetic instructions were an available option. Octal arithmetic and logic instructions were an available option.

The Core memory (@ address 00300..00399) that was freed by the replacement of the Addition table with hardware was used for storage of two selectable "bands" of seven(7) 5-digit index registers[?].

The console typewriter was replaced with a Selectric typewriter, which could type at 15 character per second.

The entire Core memory was in the IBM 1625 Memory unit. Memory cycle time was reduced to 10uS (100KHz).

The fetch/execute mechanism was completely redesigned, optimizing the timing and allowing partial fetches when the P or Q fields were not needed. Instructions took either 1, 4, or 6 Memory cycles (10uS, 40us, or 60uS) to fetch and a variable number of Memory cycles to execute. Indirect addressing added 3 Memory cycles (30uS) for each level of indirection. Indexed addressing added 5 Memory cycles (50uS) for each level of indexing. Indirect and Indexed addressing could be combined at any level of indirection or indexing.

External link

• System Reference Manual for the IBM 1620 Central Processing Unit, Model 2 (http://www.spies.com/~aek/pdf/ibm/1620/A26-5781-2_1620mod2.pdf)